Typical semiconductor memory utilized during microprocessor operation is volatile. That is in the case of power interruption, the data stored in the semiconductor memory is typically completely lost. One way to circumvent this problem is to provide separate backup of the memory, such as battery power or capacitor storage. An alternate technique is to make the memory fundamentally non-volatile. This option is highly desirable because non-volatile semiconductor memories would not only withstand power interruption, but also would be stored or shipped without being energized.
Random access memories (RAMs) enable information to be both stored and read to a memory cell as dictated by a microprocessor. Read-only-memories (ROMs), on the other hand, are memories into which information is permanently stored during fabrication and cannot be subsequently written to by a microprocessor. All ROM memory is considered non-volatile as only read operations can be performed.
Each bit of information in a ROM is stored by the presence or absence of a data path from the word (access) line to a bit (sense) line. The data path is eliminated simply by insuring no circuit element joins a word and bit line. Thus, when the word line of a ROM is activated, the presence of a signal on the bit line will mean that a 1 is stored, whereas the absence of a signal indicates that a 0 is stored.
If only a small number of ROM circuits are needed for a specific application, custom mask fabrication might be too expensive or time consuming. In such cases, it would be faster and cheaper for users to program each ROM chip individually. ROMs with such capabilities are referred to as programmable read-only-memories (PROMs). In the first PROMs which were developed, information could only be programmed once into the construction and then could not be erased. In such PROMs, a data path exists between every word and bit line at the completion of the chip manufacture. This corresponds to a stored 1 in every data position. Storage cells during fabrication were selectively altered to store a 0 following manufacture by electrically severing the word-to-bit connection paths. Since the write operation was destructive, once the 0 had been programmed into a bit location it could not be erased back to a 1. PROMs were initially implemented in bipolar technology, although MOS PROMs became available.
Later work with PROMs led to development of erasable PROMs. Erasable PROMs depend on the long-term retention of electric charge as the means for information storage. Such charge is stored on a MOS device referred to as a floating polysilicon gate. Such a construction differs slightly from a conventional MOS transistor gate. The conventional MOS transistor gate of a memory cell employs a continuous polysilicon word line connected among several MOS transistors which functions as the respective transistor gates. The floating polysilicon gate of an erasable PROM interposes a localized secondary polysilicon gate in between the continuous word line and silicon substrate into which the active areas of the MOS transistors are formed. The floating gate is localized in that the floating gates for respective MOS transistors are electrically isolated from the floating gates of other MOS transistors.
Various mechanisms have been implemented to transfer and remove charge from a floating gate. One type of erasable programmable memory is the so-called electrically programmable ROM (EPROM). The charge-transfer mechanism occurs by the injection of electrons into the floating polysilicon gate of selected transistors. If a sufficiently high reverse-bias voltage is applied to the transistor drain being programmed, the drain-substrate "pn" junction will experience "avalanche" breakdown, causing hot electrons to be generated. Some of these will have enough energy to pass over the insulating oxide material surrounding each floating gate and thereby charge the floating gate. These EPROM devices are thus called floating-gate, avalanche-injection MOS transistors (FAMOS). Once these electrons are transferred to the floating gate, they are trapped there. The potential-barrier at the oxide-silicon interface of the gate is greater than 3 eV, making the rate of spontaneous emission of the electrons from the oxide over the barrier negligibly small. Accordingly, the electronic charge stored on the floating gate can be retained for many years.
When the floating gate is charged with a sufficient number of electrons, inversion of the channel under the gate occurs. A continuously conducting channel is thereby formed between the source and drain exactly as if an external gate voltage had been applied. The presence of a 1 or 0 in each bit location is therefore determined by the presence or absence of a conducting floating channel gate in each device.
Such a construction also enables means for removing the stored electrons from the floating gate, thereby making the PROM erasable. This is accomplished by flood exposure of the EPROM with strong ultraviolet light for approximately 20 minutes. The ultraviolet light creates electron-hole pairs in the silicon dioxide, providing a discharge path for the charge (electrons) from the floating gates.
In some applications, it is desirable to erase the contents of a ROM electrically, rather than to use an ultraviolet light source. In other circumstances, it would be desirable to be able to change one bit at a time, without having to erase the entire integrated circuit. Such led to the development of electrically erasable PROMs (EEPROMs). Such technologies include NMOS transistors, floating-gate tunnel oxide MOS transistors (FLOTOX), textured high-polysilicon floating-gate MOS transistors, and flash EEPROMs. Such technologies can include a combination of floating gate transistor memory cells within an array of such cells, and a peripheral area to the array which comprises CMOS transistors.
With floating gate transistors, the floating gate polysilicon (commonly referred to as Poly 1) is positioned in between the overlying word line polysilicon (commonly referred to as Poly 2) and underlying substrate. FIG. 1 illustrates an exemplary prior art floating gate transistor construction as utilized in an array of memory cells employing non-volatile floating gate transistors. A wafer fragment 10 comprises a bulk monocrystalline silicon substrate 12 having filed oxide regions 14 provided therein. A floating gate transistor is indicated generally with numeral 15, and comprises a gate construction 16 and a pair of opposing source/drain regions 18. Gate construction 16 comprises a gate oxide or tunneling oxide layer 19, a floating gate layer 20 (typically conductively doped polysilicon), an overlying dielectric layer 21, and a wordline or control gate 22 thereatop. Gate construction 16 includes a pair of outer sidewalls 23 having an oxide layer 24 grown thermally thereover. A planarized dielectric layer 25 (typically borophosphosilicate glass or undoped SiO.sub.2 deposited by decomposition to tetraethylorthosilicate [TEOS]) is provided outwardly over gate construction 16.
Conductive regions 20 and 22 act as two plates of a capacitor. Programming of the device occurs as described above by ingesting floating gate layer 20 with a large volume of electrons. The overlying gate line 22 is thereby prevented from gating the underlying substrate channel region between source/drain diffusion regions 18. The transistor in such state is considered to be "programmed", effectively in a "zero" or "off" state.
FIG. 2 illustrates an analogous prior art construction. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix "a" or by different numerals. Transistor gate construction 16a within a wafer fragment 10a includes anisotropically etched sidewall spacers 26, typically comprising undoped SiO.sub.2 deposited by decomposition of tetraethylorthosilicate (TEOS). Source/drain regions 18a further comprise LDD regions 19. Such circuitry, at least with respect to memory integrated circuitry, would typically be utilized in control circuitry peripheral to the memory array circuitry. The FIG. 1 prior art is generally utilized within a memory array where LDD regions are not typically utilized.
One challenge in maintaining a programmed transistor in either of the above described and depicted embodiments is assuring that the electrons programmed into the floating gate layer 20 do not deplete or migrate from the floating gate. One principal pathway for such undesired migration is laterally outward of sidewalls 23. If sufficient electrons laterally migrate outward of floating gate layer 20, the transistor effectively becomes undesirably deprogrammed. The problem can be especially problematic in memory integrated circuitry having two closely adjacent gate constructions 16 having different respective programmed states. Electrons from the programmed floating gate transistor are attracted towards the floating gate of a non-programmed transistor, which adversely adds to the electron migration problem.
Further, gate construction 16 is susceptible to undesired minority carrier and other contaminate ingestion. Specifically, minority carrier "holes" emanating from other areas of operating circuitry have a tendency to migrate through insulating layer 25, through oxide layers 25 and 24 into conductive gate regions 20 and 22. Impurities likewise can physically diffuse within such regions.
It would be desirable to overcome or alleviate the above described prior art problems.